The present invention relates to a semiconductor device having a bipolar transistor with a trench.
Various types of bipolar transistors have, heretofore, been made to reduce the transistor forming region and to enhance an integrated circuit density. For example, the so-called SST type transistor was proposed by T. Sakai et al. entitled "SUPER SELF-ALIGNED BIPOLAR TECHNOLOGY" in 1983 Symposium on VLSI Technology, September 13-15, Digest of Technical papers, pp 16-19, in which the emitter region and the collector region are self-alignedly formed. On the other hand, in a bipolar transistor proposed by K. Ueno et al. entitled "A SUB-40 PS ECL CIRCUIT AT A SWITCHING CURRENT OF 1.28 MA" in IEDM 1987, Technical Digest, pp 371-374, a trench is only employed as an isolation region. In both prior art transistors, however, the N.sup.+ -type buried layer contacted to the bottom of the N.sup.- -type collector region is contacted to another N.sup.+ -type region at one side and led-out at a portion separated from a portion in which the base electrode of polycrystalline silicon is provided. Therefore, the bipolar transistors in the prior art cannot be further reduced the area of the transistor forming region and the collector resistance cannot be sufficiently decreased.